Adaptive antenna processing

ABSTRACT

Self-adapting anti-jamming device having (n + 1) sensors and enabling the restituting of the signal emitted by a source in the presence of n punctiform noise sources, comprising a combination assembly having an adder and n subtractors, an orthonormalization assembly comprising n AGC circuits, n (n - 1)/2! subtractors each combined with a correlation module, an intercorrelation set comprising n correlation modules, an adder and a subtractor.

United States Patent Giraudon 5] A r. 8 1975 [54] ADAPTIVE ANTENNA PROCESSING 3.737.783 6/l973 Oswald et al. 325/367 84.915 1 197 Id l. 325 367 [75] Inventor: Claude Giraudon, Antony, France 3 7 4 swa et a l [73] Assignee: Compagnie lndustrie'lle nes Tekfcnmmunicafions i Primary Examiner-Robert L. Griffin Pans France Assistant E.raminerMarc E. Bookbinder 2 Filed; Jam 23, 7 Attorney, Agent, or Firm-Craig & Antonelli [21] Appl. No.: 435,859

[30] Foreign Application Priority Data [-7] ABSTRACT Jan. 23, 1973 France 73.02273 521 US. Cl. 325/367- 324/77 0- 325/305- Self-adapting -ja g vice having (11 1) sen- SOIS and enabling the restituting Of the signal emitted 343/100 by a source in the presence of n punctiform noise 511 Int. Cl H04b 1/12- H04b /00 Sourccscmprising a combination assembly Ming [58] Field of Search 325/366-369 adder and n subtmcwrsi orthmormalimion assem- 325/37l 304 305 324/77 bly comprising 11 AGC circuits, [n (n l )/2] subtract- 77 5 5 6 AD 6 CL ors each combined with a correlation module, an iny tercorrelation s'et comprising n correlation modules. [56] References Cited an adder and a subtractor.

UNITED STATES PATENTS 3.652.939 3/1972 Lcvasseur 325/367 4 Claims, 9 Drawing Figures AMP FILTER VARIABLE DELAY I I I l l l I I l l l l l T1 L I I: /lj:gz 1 I IE: CORRELATION I MODULE l i PATENTEUAPR 8l975 SHEET 1 BF 5 [CORRELATION MODULE 4 5 I l I l l I l I I l l l I I I l I l I 1 2 3 2 2 y y fi G m 2 A d W X X f J N N ML A 2 6 m 1 W W mum m n E n Y m E n P T MW AMH W V 7 X X J J v M J J, A b r J F a F H 2 B h 1| |||M||I i||mw|||L 4 PATENTEDAPR ems SHEET 3 BF 5 m A B F RELATION MODULE llllllllllll llllllll l IIIIIIL AMP FILTER VARIABLE DELAY CORRELATION MODULE liiml li} PZ JEMEDAPR 8|S75 3,876,947 SHEET u (If 5 F'IG.5

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FILTER VARIABLE DE LAY MATIC SSWTROL G1 CORRELA MODULE M 1 ADAPTIVE ANTENNA PROCESSING The present invention relates to a selfadapting antijamming device having (it l sensors, :1 being a whole number greater than 1.

It is known that it is possible to manufacture receiver devices having (11 1) sensors enabling, on a basis of the signals received by these sensors, the restituting of a useful signal emitted by a source in the presence of n jammers, jamming the signal coming from the source.

The useful signal has a narrow band and a frequency f and may be an ultra-sound signal, radio-electrical signal or any other signal.

Such a device is described in the first addition No. 84,165 to French Pat. No. 1,347,229 by MERMOZ.

In the MERMOZ device, each sensor is followed by an amplifier, a filter having a narrow band centered on f0 and an element such as a delay line enabling the difference in phase between the signals coming from the source and being received by the sensors to be compensated.

At the output of the delay lines, (n l) delay signal 20, El Zn, having the form 93 o S(r) 120(1) 21 (1) bl(t) in S(r) bn(t) are obtained, 3(1) being the useful signal and b0, bl hn being noises coming from n jammers.

The MERMOZ receiver device processing the signal In, 21..., in to extract therefrom S(!) is complicated and requires a very great number of components.

It is known that Messrs. Oswald and Rainsard have simplified the MERMOZ device in the case of devices having two sensors for eliminating the noise coming from one jammer and having three sensors for canceling the noises coming from two jammers.

The receiving device having two sensors is described in French Pat. No. 70 17 868 corresponding to US. Pat. No. 3,737,783 and the receiving device having three sensors is described in French Pat. No. 70 22 l l 1 corresponding to US. Pat. No. 3,784,915.

The invention aims at generalizing and simplifying the devices of Messrs. Oswald and Rainsard.

The self-adapting anti-jamming device according to the invention enabling the eliminating of the noises emitted by the n punctiform jammers comprises:

(n l sensors, n being a whole number greater than 1, receiving a signal having a narrow band with a central frequency f0, coming from a source disturbed by jammers Circuits for processing the signals coming from the (n 1) sensors, comprising amplification means filters having a narrow band centered on f0 and delay elements sending out at their outputs (n l) signals Z0, 21... in having the form: 20 S B0 Zn S Bn S being the useful signal coming from the source and B0, B1, Bn being noises coming from the jammers:

Automatic gain control circuits AGC:

Adders:

Subtractors each comprising a input and a input: Correlation modules, COR, each module COR comprising two nonsymmetrical inputs and an output, a first input M fed by a'signal m and a second input U fed by a signal u, the output of the modul eCOR supplying a signal having the form nz.uW+ m'.1mz,nz being a signal dephased by (1r/2) in relation to the signal m; and is characterized in that it comprises:

A combination assembly comprising:

An adder J working out the sum of the various signals E0, E1 Zn and supplying a signal 2;

n subtractors D1, D2, Dn working out the difference between the signal 20 and the signals Z1, Z2, in;

An orthonormalization assembly comprising 11 channcls V1, V2 VN for processing signals coming from the subtractors D l D2 Dn and supplying n orthonormalized signals Tl, T2 Tn;

The first channel Vl comprising an AGC circuit Gl supplying at its output the signal Tl;

The input of the AGC circuit Gl being connected up to the output of the subtractor D1;

The second channel V2 comprising a subtractor D a COR module C combined with the subtractor D and AGC circuit G2 supplying at its output the signal T2;

The second V2 comprising a subtractor D a COR module C connected with the subtractor D an AGC circuit G2 supplying at its ouptut the signal T2:

The output of the subtractor D2 being connected to the input U of the COR module C and to the input of the subtractor D The output of the COR module C being connected to the input of the subtractor D The input of the AGC circuits G2 being connected to the output of the subtractor D The ptlz channel Vp, p being a whole number which may assume all the whole-number values from 2 to 11, comprising (p 1) subtractors, D D,, D,,"",j being a whole number which may assume all the values from I to p l, (p l) COR modules C C,, C,, connected with the (p l) subtractors D D, D,,", an AGC circuit Gp supplying the signal P;

The output of the subtractor Dp being connected to the inputs U of the COR modules C, and to the input of the subtractor D,,;

The output of the subtractor D,,"' being connected to the input of the subtractor D,,,

The output of the subtractor D,,"" being connected to the input of the subtractor D,,"';

The output of the COR module C,, being connected to the input of the subtractor DJ;

The output of the subtractor D,," being connected to the input of the AGC circuit Op;

The nth channel Vn comprising n l subtractors D,,, D D,,",j being a whole number which may assume all the values from 1 to n l;

(n l) COR modules C C C,,"' connected with the (n l) subtractors D D D,,"", an AGC circuit Gn supplying the signal Tn;

The output of the subtractor Dn being connected to the inputs U of the COR modules C and to the input of the subtractor D,,;

The output of the subtractor D,,"' being connected to the input of the subtractor D};

The output of the subtractor D,," being connected to the input of the subtractor D,,":

The output of the COR module C being connected to the input of the subtractor D The output of the subtractor D,,"' being connected to the input of the AGC circuit (in;

The AGC circuit G1 being connected to the inputs M of the n l COR modules C C,. C,, ,rl assuming all the whole-number values from 2 to n;

The AGC circuit Gk (k being able to assume all the whole-number values from 1 to n l being connected to the inputs M of the n k COR modules C C rk being able to assume all the whole-number values from (k l) to n,

The AGC circuit G,, being connected to the input M of the COR module C,,"

An intercorrelation assembly comprising:

n COR modules C1, C2, Cp Cn each receiving on its input M the signal T1, T2 Tp Tn and on its input U the signal 2;

An adder .1 working out the sum of the output signals of the n COR modules C1, C2 Cp Cn;

A subtractor D whose input is connected to the output of the adder B, whose input receives the signal 2 and whose output supplies the useful signal (n l) S.

The device according to the invention may be used in all detection systems for eliminating the sources of noise and more particularly in sonars.

The descriptions of the following figures given with reference to the accompanying drawings will make it easier to understand how the invention may be implemented.

FIG. 1 shows the anit-jamming device having two sensors of a known type;

FIGS. 2a, 2b, and 2c are explanatory diagrams of the operation of the anti-jamming device in FIG. 1;

FIG. 3 shows diagrammatically conventional automatic gain control circuit;

FIG. 4 shows the anti-jamming device having (n 1) sensors according to the invention;

FIG. 5 shows the anti-jamming device having three sensors according to the invention;

FIG. 6 shows a simplified AGC circuit; and

FIG. 7 shows a simplified COR module.

FIG. 1 shows the known anti-jamming device comprising a network of aerials having two sensors 10 and 20. That device is described in greater detail in French Pat. No. 7O 17 868 and only the elements required for understanding the invention will be mentioned again here. In that device, the sensor 10 is followed by an amplifier 11, a filter l2 and a variable delay line 13.

The sensor 20 is followed by an amplifier 21, a filter 22 and a variable delay line 23.

The outputs of the variable delay lines 13 and 23 are connected to the inputs of an adder 14.

The anti-jamming device comprises, also, a subtractor 24 having two inputs, a input and a input, the signal applied to the input being subtracted from the signal applied to the input.

The output of the delay line 13 is connected to the input of the subtractor 24 and the output of the delay line 23 is connected to the input of the subtractor 24.

The output of the subtractor 24 is connected to the input of an automatic gain control circuit 25 supplying a signal m.

The output adder l4 supplying a signal u and the output of the AGC circuit are connected to the two inputs U and M of a correlation module COR whose output is connected to the input of a subtractor 26 whose input is connected to the output of the adder 14.

The module COR comprises a dephaser 1 dephasing by an angle of (1r/2) whose input is connected to the input M, a first and a second multiplier 2 and 3 whose first input is connected to the output of the dephaser 1, a third and a fourth multiplier 4 and 5 whose first input is connected to the input M. The second input of the multipliers 2 and 4 is connected to the input U of the module COR. The module COR comprises, also, a first and a second integrator 6 and 7 and an adder 8.

The integrator 6 is connected up between the output of the multiplier 2 and the second input of the multiplier 3.

The integrator 7 is connected up between the output of the multiplier 4 and the second input of the multiplier 5.

The adder 8 is connected to the outputs of the multiplier 3 and 5. A signal m is applied to the input M and a signal u is applied to the input U. A signal m dephased by (17/2) in relation to m is obtained at the output of the dephaser 1.

The multiplier 2 calculates the product run of the instantaneous amplitudes of the signals u and m which, after integration in the integrator 6, supplies the signal 17. The signal am is a continuous or slowly variable signal whose magnitude is equal to the average value of the product u.m. Likewise, the signal m is obtained at the output of the integrator 7.

The multiplier 3 supplies the signal (mfm) obtained by multiplication of the signals m and m and the multiplier 5 supplies the signal (rmm).

The output signal of the adder 8 has the form (m'.um') (rum).

In the subtractor 26, the signal (mflfn?) (mm) is subtracted from the signal u and the useful signal 2 S is obtained at the output.

The directivity function of the network of aerials having two sensors (FIG. 2a) is shown in FIG. 2b.

The directivity function expresses the average amplitude 0 eff (a) with which a signal having a plane wave structure as a function of the direction of arrival of the signal relative to the axis of the aerial is rendered by the network of aerials; that function 0- eff has two zeros.

In the case where a simple sum is effected behind the delay lines 13 and 23 whose delay has been adjusted to listen in a determined direction forming an angle a with the axis of the aerial, a signal coming from the listening direction a is received with a maximum amplitude. The channel 01 has thus been formed.

The filters 12 and 22 have a narrow band and are centered on a frequency f0.

By affecting the delays of the variable delay lines 13 and 23, the listening direction of the network of aerials having two sensors may be changed.

The useful signal coming from a punctiform source situated in space, having a frequency offo, has a plane wave structure whose direction of propagation must coincide with the listening direction to ensure the best receiving.

When that coincidence has been produced, the signals Z0 and El obtained at the output of the delay lines 13 and 23 comprise a useful component having the same amplitude and the same phase and have the form:

21 S Bl S being the useful signal coming from the source and B0 and B1 being noises coming from the jammers.

This is what is done if the required signal comes from a direction coinciding with the direction 01.

lf, besides, the required signal coming from the direction a", there is an interference signal or noise coming from a punctiform jammer coming from a direction [3 different from 04, that noise is rendered by the aerial with an amplitude proportional to the value 0 01(5) of the directivity function 011 for B. Now, 0a (B) s 0a The weakening may be insufficient to enable the receiving without hindrance of the signal coming from the direction 01.

The anti-jamming device having two sensors is adapted to the noise coming from 8 by measuring its intercorrelation coefficients in order to cancel it subsequently. From the directivity point of view, this is the equivalent of displacing a zero of the directivity function up to the angle ,8.

The anti-jamming device having two sensors cancels completely the interferences which are completely correlated on the two sensors. Moreover, if the interference signal changes direction and comes from a direction 7, the device is adapted and the zero of the curve of directivity is displaced up to 'r.

The anti-jamming device, even in the presence of noises coming from jammers having any space structure effects an optimum aerial processing and enables the best signal-to-noise ratio which it is possible to obtain with an aerial having two sensors.

According to a variant of the anti-jamming device having two sensors comprising variable delay lines, P similar anti-jamming devices having in common only the two sensors, the amplifiers and the filters and whose 2P delay lines which follow are adjusted so as to fix the listening in only one direction, different for each device, may be used. It is, therefore, possible to listen sian integrator 42 at an instant T supplying a signal T 2 T 2 I xit) dt x T O and a square root extractor 43 supplying the second signal 1,.

FIG. 4 shows the anti-jamming device according to the invention comprising (n 1) sensors R0, R1 Rn each followed by an amplifier A0, A1 An, a filter F0, F1 Fn and a variable delay line L0, L1 Ln.

The sensors R0, R1 Rn are equidistant and are arranged in a straight line and the delays have been adjusted so that the listening direction coincides with the direction from which comes the useful signal coming from a punctiform source.

At the output of the delay lines are obtained it signals having the form:

2 l S Bl S being the useful signal coming from the source and B0, B1, Bn being noises coming from jammers.

The anti-jamming device comprises a combination assembly 1 consisting of an adder J working out the sum 2 of the signals Z0, Z1 Zn and n subtractors D1, D2 Dn, working out the difference between the signal 20 and the signals El, 22 Zn.

The anti-jamming device comprises also an orthonormalization assembly [I comprising n channels V1, V2 Vn for the processing of the signals coming from the subtractor D1, D2 Dn and supplying n orthonormalized signals T1, T2 Tn.

The first channel V1 comprises an AGC circuit G1 supplying at its output the signal T1, the input of the AGC circuit Gl being connected to the output of the subtractor D1.

The second channel V2 comprises a subtractor D 21 COR module C connected with the subtractor D an AGC circuit G2 supplying at its output the signal T2.

The output of the subtractor D2 is connected to the input U of the COR module C and to the input of the subtractor D The output of the COR module C being connected to the input of the subtractor D The input of the AGC circuit G2 being connected to the output of the subtractor D The p channel Vp, p being a whole number which may assume all the values from 2 to it comprises (p l subtractors, D,, D m, D,,,j being a whole number which may assume all the values from 1 to p l, (p-l) COR module C C C,,"' connected with the (p-l) subtractors D,,..., D,, D,,", AGC circuit Gp supplying the signal Tp.

The output of the subtractor D is connected to the inputs U of the COR modules C at the input of the subtractor D,,.

The output of the subtractor D is connected to the input of the subtractor D}.

the output of the subtractor DJ is connected-to the input of the subtractor D,,"".

the output of the COR module C is connected to the input of the subtractor DJ.

The output of the subtractor D being connected to the input of the AGC circuit Op.

The n"' channel Vn comprises (nl subtractors D D D,," ,j being a whole number which may assume all the values from 1 to n1), (n-l COR modules C Cn CH connected with the (n-l) subtractors D ...D,, ...Dn"- an AGC circuit Gn supplying the signal Tn.

the output of the subtractor Dn being connected to the inputs U of the COR modules C,, and to the input of the subtractor D,,,

The output of the subtractor D,,"' is connected to the input of the subtractor D The output of the subtractor D,,"' is connected to the input of the subtractor D,,"".

The output of the COR module C, is connected to the input of the subtractor D,,.

The output of the subtractor D,,"" is connected to the input of the AGC circuit Gn.

the AGC circuit G1 is connected to the input M of the n l COR modules C C C rl assuming all the whole number values from 2 to n.

The AGC circuit Gk (k being able to assume all the whole number values from 1 to n l) is connected to the inputs M of the n k COR modules C C C rk being able to assume all the whole number values from (k+l) to n.

The AGC circuit G n-l is connected to the input M of the COR module C,,"

The anti-jamming device comprises, moreover, an intercorrelation assembly 11] comprising: nCOR modules C1, C2, Cp Cn, each receiving on its input M the signal T1, T2 Tp Tnand on its input U the signal 2, and adder J working out the sum of the output signals of the n COR modules C1, C2 Cp C11 and a subtractor D whose input is connected to the output of the adder J, whose input receives the signal 2 and whose output supplies the useful signal (n+1 )5.

By means of the device according to the invention. :1 zeros of the directivity curve of the network of aerials having (n+1) sensors may be moved and hence the noises coming from the n punctiform jammers may be canceled. in the presence of noises coming from jammers having a nondescript space structure, the device according to the invention effects an optimum serial processing and enables the obtaining of the best signalto-noise ratio possible with an aerial having (n+1) sensors.

FIG. shows the anti-jamming device according to the invention having three sensors, each of the sensors R0, R1, R2 is followed by an amplifier A0, A1, A2, by a filter centered on a frequency f0, F), F1. F2 and by a variable delay line L9, L1, or L2.

The delay lines L0, L1, L2 send out to their outputs three signals Z0, Z1, 22 having the form:

S Bo El S B1 22 S B2 S being the useful signal coming from the source and B0, B1, B2 being noises coming from the jammers.

The anti-jamming device comprises an adder J carrrying out the sum of the three signals 20, El, 22 and two subtractors D1 and D2 working out the difference between the signal 20 and the signals 21 and E2.

The output of the subtractor D1 is applied to the input of an AGC circuit G1 and the output ofGl is applied to the inputs M of a COR module Cl and of a COR module C The output of the subtractor D2 is applied to the input U of the COR module C and to the+ input of a subtractor D the input of the subtractor D being connected to the output of the COR module C2.

The output of the subtractor D is connected to the input of an AGC circuit G2 whose output is connected to the input M off a COR module C2.

The inputs U of the COR module C1 and C2 are connected to the output of the adder J. The outputs of the COR modules Cl and C2 are connected to the inputs of an adder J whose output is connected to the input of subtractor D. l

The input of the subtractor D is connected to the output of the adder J and the output of the subtractor D supplies the useful signal 35.

The anti-jamming device having three sensors according ot the invention therefore comprises, starting from the delay lines: two AGC circuits, three COR modules, two adders and four subtractors.

The anti-jamming device having three sensors such as described in French Pat. No. 70 22 111 corresponding to US. Pat. No. 3,784,915 comprises a dephaser, three adders, five subtractors, six AGC circuits, two COR modules having their adder in common.

The antijamming device having three sensors according to the invention therefore makes it possible to save four AGC circuits, a subtractor and a dephaser but requires an extra COR module.

As the square root extractor, the quadratic detectors, the multipliers and dividers are hardware devices whose complexity is much greater than the summing machines and the subtractors, it will be seen that a COR module represents much less hardware than four AGC circuits, so'much that the anti-jamming device having three sensors according to the invention and even more the device having n+ 1 sensors, is an improvement in relation to the device having three sensors according to French Pat. No. 22 Ill corresponding to US. Pat. No. 3,784,915.

In the case where the noises are gaussian, it is possible to simplify, in the anti-jamming device according to the invention, the AGC circuits and the COR module and therefore to reduce the size of the hardware.

FIG. 6 shows a simplified automatic control AGC circuit which may be used in the anti-jamming device according to the invention when the noises are gaussian.

The simplified AGC circuit comprises a divider 40' receiving on an input a first signal .\'(I) and on the other input a sound signal calculated on a basis of the said first signal by a linear detector 41' followed by an integrator 42.

FIG. 7 shows a simplified COR module which may be used in the anti-jamming device according to the invention when the noises are gaussian.

The simplified COR module comprises the same elements as the COR module shown in FlG. l, with the exception of the first and third multipliers, which are replaced by switches 2 and 4 and comprise two peak limiters 2" and 4 arranged before one of the inputs of each switch so as to limit the peaks of the analog signals coming from the input M. v

The peak limiters transform the said analog signals into binary signals representative of the sign of the analog signals.

The simplified COR module comprises, like the COR module shown in FIG. 1, the two multipliers 3 and 5, the integrators 6 and 7, the dephaser l dephasing by an angle of (1r/2) and the adder 8.

It is possible, instead of using the variable delay lines in the anti-jamming devices according to the invention, to take a number P of similar anti-jamming devices having in common only the (n+1) sensors and the amplifiers and filters which follow them and whose delay lines are adjusted permanently differently for each device so that it be possbile to listen in P different directions.

It is also possible to arrange the n+1 sensors in a nondescript way provided that the variable delay lines be adjusted so as to receive the signals coming from a given direction with the maximum of sensitivity.

Although the anti-jamming devices which have just been described appear to afford the greatest advantages, it will be understood that various modifications may be made thereto without going beyond the scope of the invention, it being possible to replace certain of their elements by other elements capable of providing the same function or an equivalent technical function therein.

What is claimed is:

l. A self-adapting anti-jamming device receiving a signal having a narrow band with a central frequency coming from a signal source disturbed by a plurality of jammers, comprising (n +1 sensors receiving said signal, where n is an integer greater than 1, a plurality of amplifiers each connected to a respective sensor, a plurality of narrow band filters having a pass band centered on said central frequency and each connected to the output ofa respective amplifier, a plurality of delay elements each connected to the output of a respective filter and providing at the output thereof the sum of the useful portion of said signal from said signal source and the noise from a respective one of said jammers,

a first adder having inputs connected to the outputs of all of said delay elements, it first subtractors each having a positive input connected in common to the output of one of said delay elements and a negative input connected to the output of a respective one of the other delay elements.

a sequence of channels each connected to the output of a respective one of said first subtractors, the first channel of the sequence comprising an automatic gain control circuit and each other channel of the sequence comprising a number of serially connected subcombinations equal to the number of the channel in the sequence less one in series with an automatic gain control circuit, said subcombinations. each comprising a second subtractor having a positive input receiving the output of its respective first subtractor and a negative input receiving the output of a first correlation unit having one input connected to the positive input of said second subtractor and another input connected to the output of an automatic gain control circuit in a respective one of the preceeding channels of the sequence, said automatic gain control circut in each of said other channels has an input connected to the output of the second subtractor in the last of said serially connected subcombinations and a pluralilty of second correlation units each having one input connected in common to the output of said first adder and a second input connected to the output ofa respective channel, a second adder connected to the outputs of said second correlation units, and a third subtractor having a possible input connected to the output of said first adder and a negative input connected to the output of said second adder.

2. An anti-jamming device as defined in claim 1 wherein said automatic gain control circuit each comprise a divider having a first input connected to the output of a second subtractor in the channel. a linear detector having an input connected to the first input of said divider, and an integrator connected between the output of said detector and a second input of said divider.

3. An anti-jamming device as defined in claim 1 wherein each correlation unit comprises first and second circuits each including a peak limiter, a switch between the output of said switch and having one input connected to the output of said peak limiter and an integrator connected one input of a multiplier, the other input of the multiplier being connected to the input of said peak limiter, a phase shifter being connected to the input of the peak limit in said first circuit and a third adder having respective inputs connected to the outputs of the multipliers in said first and second circuits. said one input of each correlation unit being connected to a second input of each of said switches of said first and second circuits thereof and other input being connected to the input of said phase shifter and the input of the peak limiter of said second circuit thereof.

4. An anti-jamming device as defined in claim 1 wherein each correlation unit comprises means responsive to a signal it on said one input and a signal m on said other input for supplying an output m,u m

m.u m',m' being the signal m shifted in phase by (1r/2). "K :K 4 5 UNITED STATES PATENT OFFICE CERTIFICATE OF' CORRECTION Patent No. ,947 Dated April 1975 Inventor(s) Claude Giraudon Page 1 of 2 It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Figure 4, should appear as shown on the attached sheet.

Signed and Scaled this twenty-fifth Day Of May 1976 {SEAL} Arrest:

RUTH C. MASON C. MARSHALL DANN Arresting Officer Commissioner nj'larems and Trademarks 

1. A self-adapting anti-jamming device receiving a signal having a narrow band with a central frequency coming from a signal source disturbed by a plurality of jammers, comprising (n +1) sensors receiving said signal, where n is an integer greater than 1, a plurality of amplifiers each connected to a respective sensor, a plurality of narrow band filters having a pass band centered on said central frequency and each connected to the output of a respective amplifier, a plurality of delay elements each connected to the output of a respective filter and providing at the output thereof the sum of the useful portion of said signal from said signal source and the noise from a respective one of said jammers, a first adder having inputs connected to the outputs of all of said delay elements, n first subtractors each having a positive input connected in common to the output of one of said delay elements and a negative input connected to the output of a respective one of the other delay elements. a sequence of channels each connected to the output of a respective one of said first subtractors, the first channel of the sequence comprising an automatic gain control circuit and each other channel of the sequence comprising a number of serially connected subcombinations equal to the number of the channel in the sequence less one in series with an automatic gain control circuit, said subcombinations each comprising a second subtractor having a positive input receiving the output of its respective first subtractor and a negative input receiving the output of a first correlation unit having one input connected to the positive input of said second subtractor and another input connected to the output of an automatic gain control circuit in a respective one of the preceeding channels of the sequence, said automatic gain control circut in each of said other channels has an input connected to the output of the second subtractor in the last of said serially connected subcombinations and a pluralilty of second correlation units each having one input connected in common to the output of said first adder and a second input connected to the output of a respective channel, a second adder connected to the outputs of said second correlation units, and a third subtractor having a possible input connected to the output of said first adder and a negative input connected to the output of said second adder.
 2. An anti-jamming device as defined in claim 1 wherein said automatic gain control circuit each comprise a divider having a first input connected to the output of a second subtractor in the channel, a linear detector having an input connected to the first input of said divider, and an integrator connected between the output of said detector and a second input of said divider.
 3. An anti-jamming device as defined in claim 1 wherein each correlation unit comprises first and second circuits each including a peak limiter, a switch between the output of said switch and having one input connected to the output of said peak limiter and an integrator connected one input of a multiplier, the other input of the multiplier being connected to the input of said peak limiter, a phase shifter being connected to the input of the peak limit in said first circuit and a third adder having respective inputs connected to the outputs of the multipliers in said first and second circuits, said one input of each correlation unit being connected to a second input of each of said switches of said first and second circuits thereof and other input being connected to the input of said phase shifter and the input of the peak limiter of said second circuit thereof.
 4. An anti-jamming device as defined in claim 1 wherein each correlation unit comprises means responsive to a signal u on said one input and a signal m on said other input for supplying an output m,um + m''.um'', m'' being the signal m shifted in phase by (.pi./2). 